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Doing High-level Synthesis ?

Is RTL *coverage* a requirement?

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A case study of using JEDAcc for HLS

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8051 Processor

- 800+ lines of C code
- 8-bit uP
- 4k program memory,
- 128 byte data memory
- up to 64k external memory

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8051 Testbench

sort, fib, xram, all

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Measure code coverage at HL using JEDA

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Measure coverage using other tools: 88%

*False High*

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Using JEDA HW-Aware coverage product JEDAcc: Only 25%

JEDA uncovers coverage holes others can't

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Measure code coverage for RTL model

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Measure RTL Coverage

- Line coverage at 85%

- Decision coverage at 78%

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Correlation between HL & RTL

RTL coverage grows with HL as TB improves and new tests added

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Conclusions

- *HW-aware* Coverage generates similar results to RTL

- Remove *Verification* weak link in HLS flow

- RTL coverage is redundant for HLS

- Move verification to high level, 10x-100x faster

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JEDA Model Validation Solution

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